1. Field of the Invention
The present invention relates to a passive matrix-addressable memory apparatus.
2. Description of the Related Art
Since ions or molecules are arranged in a specific direction in ferroelectric or electret materials used as memory materials in even a state that an external voltage is not applied, they have polarization. Such ferroelectric or electret materials maintain two stable states by polarization. Two stable states are regarded as logic states ‘0’ and ‘1’. Accordingly, the ferroelectric or electret materials have been applied to a non-volatile memory device using polarization.
A capacitor may be formed of an electrode/ferroelectric or electret/electrode structure using ferroelectric or electret materials as dielectric materials. Upon applying an operation voltage Vs greater than a coercive voltage ‘Vc’ to both electrodes of the capacitor, referring to FIG. 1, the both electrodes of the capacitor enters a saturated polarization Ps state according to a hysteresis loop. Meanwhile, when a voltage is not applied to the capacitor, the capacitor remains in a remanent polarization Pr state, which may be regarded as one of logic states ‘1’ and ‘0’. Likewise, upon applying an operation voltage −Vs having a polarity opposite to Vs to both electrodes of the capacitor, the both electrodes thereof enter a saturated polarization state of −Ps. In the meantime, when a voltage is not applied to the both electrodes of the capacitor, it remains in a remanent polarization state, thereby changing a previous logic state.
FIG. 2 is a view illustrating a conventional passive matrix memory device 200 using ferroelectric or electret materials.
Referring to FIG. 2, the conventional passive matrix memory device 200 includes a memory layer 210 made of ferroelectric or electret materials, a plurality of bit lines 220 arranged parallel to each other at an upper portion of the memory layer 210, and a plurality of word lines 230 arranged orthogonal to the bit lines 220 parallel to each other at an under portion of the memory layer 210.
The bit lines 220 and word lines 230 are arranged orthogonal to each other. Further, ferroelectric and electret materials are formed between the bit lines 220 and the word lines 230. Referring to FIG. 3, accordingly, one memory cell having a bit line 220/ferroelectric material or electret material 210/word line 230 structure is provided at an intersection point (j, k) of the bit line 220 and the word line 230. It is easy to manufacture the conventional passive matrix memory device 200. Since the conventional passive matrix memory device 200 has a smaller number of transistors in comparison with an active matrix memory device, it may perform high-density storage.
The conventional passive matrix memory device 200 is driven in such a way that data are stored, and erased or read in and from a memory cell disposed at an intersection of the specific word line and the specific bit line by applying a voltage pulse to a specific word line and a specific bit line so as to select a desired memory cell. However, such a driving method may cause electric interference in memory cells that are not selected. The electric interference may destroy data stored in the memory cells, which are not selected.
In order to solve the problems, there has been proposed a method reducing electric interference based on ⅓ voltage selection rule in a driving method of the conventional memory device. FIG. 4 is a view illustrating a ⅓ voltage selection rule. The ⅓ voltage selection rule causes only ⅓ of an operation voltage Vs to be applied to bit lines and word lines of memory cells that are not selected, thereby influencing the memory cells a little by electric interference. In this case, Vs/3 being ⅓ voltage means a voltage less than a coercive voltage of a ferroelectric or electrets material.
However, there are problems in the ⅓ voltage selection rule. For example, in a state that data having logic state ‘1’ are stored in a memory cell, when ⅓ operation voltage Vs/3 according to the ⅓ voltage selection rule having a polarity capable of writing logic state ‘0’ is continuously applied to a specific memory cell, a logic state of a specific memory cell can be changed to a state opposite to a previous state. Namely, the specific memory cell can be changed from a previous logic state ‘1’ to a logic state ‘0’. Meanwhile, in a state that data having a logic state ‘0’ are stored in the specific memory cell, if ⅓ operation voltage Vs/3 having a polarity capable of writing a logic state ‘1’ is continuously applied thereto, the logic state of a specific memory cell can be also changed to a state opposite to a previous state. Korean patent laid-open publication No. 10-2007-0094646 defines such a phenomenon as disturbing. In the meantime, the document “Japanese Journal of Applied Physics, Vol. 36(1997), pp. 1655 (H. Ishiwara)” experimentally approved the disturbing using SBT being a ferroelectric inorganic material. The experiment shows that upon continuously applying a voltage pulse of Vs having a polarity capable of inverting a logic state to a specific memory cell, a logic state of stored data is inverted. Moreover, the document explained that the less an interference voltage is, the longer data is maintained.
Hereinafter, disturbing or electric interference according to a ⅓ voltage selection rule will be described in detail.
Referring to FIG. 2, the conventional memory device 200 includes a memory unit 210, N bit lines 220, and M word lines 230. A specific memory cell of the conventional memory device 200 is expressed by ‘(j, k) cell’ for convenience sake.
In order to write data in entire memory cells of the conventional memory device 200, M×N bit data should be stored. For example, data are written in a (1, 1) cell by applying a voltage to a first word line and a first bit line. In this case, a voltage having amplitude of ⅓ of a voltage capable of writing data is applied to all remaining memory cells except for a (1, 2) cell. There does not cause a problem in a memory cell that is not written yet. A firstly written (1, 1) cell has electric interference with ⅓ voltage from a second write. Accordingly, a (1, 1) cell has electric interference (M×N)−1 times until data are written in an (N, M) cell being a final cell. The passive matrix-addressable memory device is advantageous in that it can perform high-density storage. Accordingly, N and M is significantly greater than 1, each time a write operation is performed, a (1, 1) cell inevitably has electric interference as much as a storage capacity of a memory device.
Interference occurs in a data reading operation as well as a data writing operation in the passive matrix memory device 200. Because each memory cell does not have an active device, it is impossible to non-destructively read data stored in a memory cell. Consequently, after destructive-reading data, a write operation should be again performed. In memory cells in which a rewrite operation is performed after reading data, even a little polarization loss occurs in a previous step, a previously written logic state may be maintained through a rewrite procedure. However, non-read memory cells are inevitably exposed to an interference voltage as many as the number of read memory cells.
So as to solve electric interference occurring due to a ⅓ voltage selection rule, there was suggested a method for dividing a passive matrix based memory of large storage capacity into a plurality of small segments in Patent No. 20035225 by Thin Film Electronics ASA. Upon dividing a memory cell into a plurality of segments, because a specific segment is electrically and physically isolated from other segments during a write operation to the specific segment, electric interference does not occur. The more the number of the segments are, the less the applied number of an interference voltage can be. However, because the same number of active devices is additionally required by the corresponding number of word lines and bit lines every segment, high-density storage capacity being the greatest merit of the passive matrix addressable arrangement is removed.
Meanwhile, so as to solve electric interference occurring due to a ⅓ voltage selection rule, there was suggested a refresh function in Korean patent laid-open publication No. 10-2007-0094646. In the patent, an interference voltage is applied the same number of times as the number of memory cells writing data. Accordingly, if a counter counts the any number of events to write the events, all data written in a specific segment are rewritten. The patent may reduce data loss due to electric interference but cannot fundamentally stop it. As a result, a fundamental method reducing electric interference is to reduce an amplitude of a voltage applied to both ends of a memory cell storing data.